1. Description of Related Art
The present invention relates generally to data transfer from a host system to a SCSI target, and more particularly, to reducing the latency associated with a data transfer from a host system to a target device via a host adapter.
2. Description of Related Art
Host adapter integrated circuits, sometimes called host adapters, were widely used for interfacing two I/O buses such as a host computer I/O bus and a SCSI bus. FIGS. 1A and 1B are representations of data paths through a prior art host adapter 100 for transfer of data from a host system 180 to a SCSI target device in a plurality of SCSI target devices 191, 192, 193.
In a data transfer from host system 180 to a SCSI target device, it was sometimes desirable to cache the data on host adapter 100. The advantage of caching the data was that the data was transferred only once over host I/O bus 181.
Prior art caching host adapters, such as host adapter 100, required that all the data for a write operation to a SCSI target device be cached in data caching memory 160 before host adapter 100 sent a write command to the SCSI target device. When very many commands are queued in host adapter 100, data for a new write command for a particular SCSI target device was cached in memory 160 while previous commands for that particular SCSI target device were executed. In this case, multiplexer 111 was configured by direction control module 170 to transfer data from host I/O bus 181 to host DMA engine 120. Multiplexer 113 was configured by direction control module 170 to transfer data from host DMA engine 120 to data caching memory 160.
For this situation, the data was transferred only once over host I/O bus 181. When the target device was ready to execute the new write command, the cached data was transferred from memory 160 through multiplexer 113 to multiplexer 112 and through multiplexer 112 to first-in-first-out (FIFO) memory 140. The data was transferred from FIFO memory 140 through SCSI module 150 to the SCSI target device. Thus, when the SCSI target device was ready to receive the data from the new write command, the data was available from data caching memory 160 with virtually no latency.
However, a problem arose when there were not enough commands queued in host adapter 100 to permit overlapping execution of one command for a SCSI target device with caching data, for another command, in memory 160 for that SCSI target device. If the SCSI target device had to wait for the caching of the data, i.e., wait until the data had been completely transferred from host system 180 to memory 160, the latency for providing the data to the target was considerable.
To remove this latency, the data path illustrated in FIG. 1B was used. When a target was ready to receive data and the data was not cached in memory 160, host adapter 100 connected host I/O bus 180 directly to target DMA engine 130 through multiplexers 111 and 112. Hence, the data was transferred directly from the host buffer memory to FIFO 140. While this technique removed the latency of waiting for all the data to be cached in memory 160, the technique degraded the utilization of host I/O bus 181, because the same data had to be transferred across bus 181 when that data was written to multiple SCSI target devices. Consequently, host adapter 100 required either suffering the latency penalty of waiting for all the data to be cached, or alternatively, degrading the utilization of the host system I/O bus.